Semiconductor devices containing CMOS circuits having PMOS and NMOS transistors are capturing attention.
In those semiconductor devices, a gate conductor is formed continuously in a PMOS transistor formation region and an NMOS transistor formation region. The portion of the gate conductor in the PMOS transistor formation region works as the gate electrode of the PMOS transistor; the portion of the gate conductor in the NMOS transistor formation region works as the gate electrode of the NMOS transistor.
Over the semiconductor substrate on which the PMOS and NMOS transistors are formed, an interlayer insulating film is formed to cover the PMOS and NMOS transistors. Contact holes to the gate conductor are formed in the interlayer insulating film and conductor plugs are embedded in the contact holes.
There is a method for improving the carrier mobility in a PMOS transistor by providing an insulating film that covers the PMOS transistor so as to apply a compressive stress to the channel region of the PMOS transistor. In another method for improving the carrier mobility in an NMOS transistor, an insulating film that covers the NMOS transistor is formed so as to apply a tensile stress to the channel region of the NMOS transistor. (See Japanese Laid-Open Patent Publications No. 2007-208166, No. 2008-16853 and No. 2007-235074, for example).
However, when forming contact hole down to the gate conductor passing through the stress insulating films, the hole may not reach the gate conductor because of the stress insulating films. If contact holes do not reach the gate conductor, the connection between the conductor plugs and the gate conductors may not be ensured and a sufficiently high manufacturing yield may not be achieved.